CAN Core

The CAN Core is a CAN module that can be integrated as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis.

The CAN Core performs communication according to the CAN Protocol Version 2.0 Part A and B. The bitrate can be configured to values up to 1MBit/s depending on the used technology. For the connection to the physical layer additional transceiver hardware is required.

The CAN Core consists of CAN Protocol Controller and Rx/Tx Shift Register. No permanent Message Buffer is implemented. All functions concerning the handling of messages like acceptance filtering, transfer of messages between the Shift Register and the Message Buffers, as well as the handling of transmission requests and the generation of the module interrupt have to be implemented separately. The interface to the external Message Handler is designed to be as flexible and simple as possible with respect to integration of the cell into different environments. Received messages can be read in parallel from the CAN Core. Acceptance filtering can be started directly after reception of the arbitration and control field. Messages to be transmitted may be loaded into the Shift Register in parallel or sequentially in blocks of at least one byte.

The CAN Core is available in two different packages. The first package comes with a set of reference pattern for the verification of the CAN Core module in a user-defined application. The second package includes the BOSCH VHDL Reference CAN model to give the user access to the complete VHDL Reference testbench.